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Control Loop and Frequency Response

Closed loop control is the basis of many electronic and electrochemical systems. Quantifying for example the stability of a power supply control loop, requires a combination of frequency selectivity, dynamic range, noise immunity and phase accuracy that only a dedicated frequency response analyzer can provide.

Loop Response Design and Test

Given the objective of a power supply to maintain a defined output, most power supplies are regulated.

Regulation involves the comparison of a power supply output with a reference, then adjusting a gain stage within the power supply to maintain the desired output.

‘Loop response analysis’ or ‘frequency response analysis’ is the characterisation of a control loop by relative gain and phase between two points over a range of frequencies.

Swith Mode Power Supply (SMPS)

Loop Stability

Control loop measurement showing gain and phase margin

The result of loop response tests is usually presented as either a ‘Bode’ or ‘Nyquist’ plot that will enable an engineer to confirm regulation and stability of a power supply in response to load change.

This method overcomes the subjectivity of waveform observation during a step load change, by providing a clearly defined and quantifiable stability test using absolute and measurable gain and phase margin targets over a defined frequency range.

Commonly recognised margins for a stable power supply are -20dB Gain Margin when loop phase is zero, and 45 Degree Phase Margin when loop gain is 0dB.

Signal Injection

Control loops are most commonly tested by adding or ‘injecting’ a disturbance signal into the loop and then using a measurement device that can measure relative gain and relative phase of the injected signal at two points in the loop.

Signal injection should ideally be within a high impedance feedback part of a loop to ensure signal injection and measurement hardware has minimal impact on the loop it is testing, and it follows that the disturbance signal source should be isolated, so that the residual voltage at that point in a circuit is not disturbed.